Timed CSP Simulator
نویسندگان
چکیده
Time is an integral aspect of computer systems. It is essential for modelling a system’s performance and also affects its safety or security. Timed Csp [5] conservatively extends the process algebra CSP with timed primitives, where real numbers ≥ 0 model how time passes with reference to a single, conceptually global, clock. While there have been approaches for model checking Timed Csp [1, 5], the simulation of Timed Csp was considered only recently [2, 6]. In this poster, we highlight the architecture and a number of selected features of our Timed Csp Simulator, which is a consolidated, mature version of the research prototype presented in [2].
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